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- [2] Copper Electrodeposition Parameters Optimization for Through-Silicon Vias Filling PROCESSING, MATERIALS, AND INTEGRATION OF DAMASCENE AND 3D INTERCONNECTS, 2010, 25 (38): : 109 - 118
- [4] Pretreatment to assure the copper filling in through-silicon vias Journal of Materials Science: Materials in Electronics, 2016, 27 : 7460 - 7466
- [7] Thermo-Mechanical and Electrical Characterization of Through-Silicon Vias with a Vapor Deposited Polyimide Dielectric Liner 2012 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE (IITC), 2012,
- [8] Influence of Copper Pumping on Integrity and Stress of Through-Silicon Vias IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2016, 6 (08): : 1221 - 1225