A novel open-loop high-speed CMOS sample-and-hold

被引：13
|
作者：
Mousazadeh, Morteza [1 ]
Hadidi, Khayrollah [1 ]
Khoei, Abdollah [1 ]
机构：
[1] Urmia Univ, Microelect Res Lab, Orumiyeh 53139, West Azerbaijan, Iran
来源：
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS | 2008年 / 62卷 / 08期
关键词：
sample and hold; ADC; charge injection; linearity;
D O I：
10.1016/j.aeue.2007.08.003
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A new open-loop high-speed CMOS sample-and-hold is presented. Based on new method for further reduction of voltage-dependent charge injection, a new CMOS sample-and-hold was designed. Simulation results confirm the effectiveness of this method. Over 10dB improvement in signal-to-noise ratio, compared to the signal-to-noise ratio of conventional bottom plate sampling S/Hs was achieved with this method. A comparison between newly designed S/H and the bottom-plate sampling S/H is presented. (c) 2007 Elsevier GmbH. All rights reserved.
引用
收藏
页码：588 / 596
页数：9
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