Passive filter aided timing recovery scheme

被引：0

作者：

Musa, Faisal A. ^{[1
]}

Carusone, Anthony Chan ^{[1
]}

机构：

[1] Univ Toronto, Edward S Rogers Sr Dept Elect & Comp Engn, Toronto, ON M5S 3G4, Canada

来源：

PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10 | 2008年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a passive filter for the front end of a high speed serial link receiver to aid timing recovery. The filter provides simultaneous lowpass and highpass transfer characteristics to generate the data and its slope respectively. Slope detection is demonstrated at 10-Gb/s. As a proof of concept, the filter was used to extract a 2-GHz clock from a 2-Gb/s 2(31)-1 random data sequence based on a modified minimum mean squared error (MMSE) criterion. The circuit is fabricated in a 0.18 mu m CMOS process and consumes 21.6 mW from a 1.8V supply.

引用

页码：3065 / 3068

页数：4

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