Design of a 2D Median Filter with a High Throughput FPGA Implementation

In this paper, a hybrid technique for median filtering of images affected by impulse noise is proposed. Our technique combines impulse noise detection, histogram-based median calculation and bit-plane processing to obtain approximate median with the aim of optimizing the throughput at minimum cost of image quality. The proposed median filter is implemented on FPGA with pipelining and is significantly faster than existing FPGA based pipelined median filter architectures. Implementation of the proposed median filter hardware provides a throughput of 282 Full High Definition (FHD) frames per second on Zynq-7 FPGA; 48% higher than the throughput of low-latency median filter. Compared to FPGA implementation of a low complexity noise removal, the proposed median filter utilizes only 45% of FPGA slices and provides a speed-up of 2.2 on Zynq-7 FPGA.