MULTIDIMENSIONAL DATAFLOW GRAPH MODELING AND MAPPING FOR EFFICIENT GPU IMPLEMENTATION

被引：1

作者：

Wang, Lai-Huei ^{[1
]}

Shen, Chung-Ching ^{[1
]}

Seetharaman, Gunasekaran ^{[2
]}

Palaniappan, Kannappan ^{[3
]}

Bhattacharyya, Shuvra S. ^{[1
]}

机构：

[1] Univ Maryland, Dept Elect & Comp Engn, College Pk, MD 20742 USA

[2] Air Force Res Lab, Rome, NY USA

[3] Univ Missouri Columbia, Columbia, MD USA

来源：

2012 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS) | 2012年

关键词：

Dataflow graph; multidimensional synchronous dataflow; graphics processing unit; integral histogram;

D O I：

10.1109/SiPS.2012.10

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Multidimensional synchronous dataflow (MDSDF) provides an effective model of computation for a variety of multidimensional DSP systems that have static dataflow structures. In this paper, we develop new methods for optimized implementation of MDSDF graphs on embedded platforms that employ multiple levels of parallelism to enhance performance at different levels of granularity. Our approach allows designers to systematically represent and transform multi-level parallelism specifications from a common, MDSDF-based application level model. We demonstrate our methods with a case study of image histogram implementation on a graphics processing unit (GPU). Experimental results from this study show that our approach can be used to derive fast GPU implementations, and enhance trade-off analysis during design space exploration.

引用

页码：300 / 305

页数：6

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