Avalanche photodiode array in BiCMOS technology

Avalanche photodiode (APD) imaging arrays offering programmable gain are a long awaited achievement in electronic imaging. In view of the recent boom in CMOS imaging, a logical next step for increasing responsivity was to integrate APDs in CMOS. Once the feasibility of these diodes has been proven, we can combine the devices with control and readout circuitry, thus creating an integrated 2D APD array. Such arrays exploit the sub-Geiger mode, where the applied voltage is just slightly less than the breakdown voltage. The diodes used in the 2D array were implemented in a standard 2 mu m BiCMOS process. To keep the readout circuitry simple, a small transimpedance amplifier has been designed, taking into account that there is a significant trade off between noise performance and silicon area. As with other CMOS imagers, we use a random access active pixel sensor readout. The complete imaging array consists of 12 by 24 pixels, each of size 71.5 mu m by 154 mu m to fit on a 5 mm(2) chip. First images prove the feasibility of avalanche photodiode imaging using standard BICMOS technology. Thus important data to improve sensor operation has been collected. The complexity of the imager design is increased by special noise and high voltage requirements. Area and calibration restrictions must be considered also for this photo-sensor array.