Bias-Engineered Mobility in Advanced FD-SOI MOSFETs

Ground-plane (GP) biasing in fully depleted siliconon-insulator (FD-SOI) MOSFETs allows not only the tuning of the threshold voltage, but also the mobility improvement. We study the carrier mobility enhancement by introducing the return point (or minimum value) of the effective field. This parameter defines the optimum GP bias condition to maximize the mobility gain. Different regions of operation can be discriminated according to the monotonic increase or decrease of the effective field with the front-gate bias. For large mobility enhancement, the return point voltage V-ret is adjusted via GP bias such as to exceed the threshold voltage. Experimental results show mobility gains over 70% in SOI MOSFETs with ultrathin buried oxide (10 nm) and Si film (8 nm).