DAC calibration by weighting capacitor rotation in a pipelined ADC

The design flow of a pipelined ADC with DAC errors correction in the first stages requires tayloring the digital correction hardware to the process dependent uncertainties affecting the weighting elements, which can be better appreciated on first silicon. The described FPGA implementation of the correction hardware allows flexible and quick co-development of the analog and digital sections of the converter. A novel error correction scheme based on weighting capacitor rotation is applied.