A 100-MHz, 16-b, direct digital frequency synthesizer with a 100-dBc spurious-free dynamic range

被引：111

作者：

Madisetti, A ^{[1
]}

Kwentus, AY

Willson, AN

机构：

[1] Broadcom Corp, Irvine, CA 92618 USA

[2] Pent Inc, Pasadena, CA 91107 USA

[3] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90095 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1999年 / 34卷 / 08期

关键词：

CMOS integrated circuit design; direct digital synthesizers; frequency synthesizers; very large-scale integration (VLSI) for digital communications;

D O I：

10.1109/4.777100

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes the architecture and the IC implementation of a direct digital frequency synthesizer (DDFS) that is based on an angle rotation algorithm (similar to CORDIC), It is shown that the architecture can be implemented as a multiplierless, feedforward, and easily pipelineable datapath, A prototype IC has been designed, fabricated in 1.0-mu m CMOS, and tested. The IC produces 16-b sine and cosine outputs with a spurious-free dynamic range of more than 100 dBc. A 36-b frequency control word gives a tuning resolution of 0.0015 Hz at a 100-MHz sampling rate.

引用

页码：1034 / 1043

页数：10

共 7 条

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SAUL, PH
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1988, 23 (03) : 819 - 821
[2] 100-MHz CMOS direct digital synthesizer with 10-bit DAC
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APCCAS 2002: ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS, 2002, : 385 - 388
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[5] Theoretical upperbound of the spurious-free dynamic range in direct digital frequency synthesizers realized by polynomial interpolation methods
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2007, 54 (10) : 2252 - 2261
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (11) : 1853 - 1861

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