A low-area decimation filter for ultra-high speed 1-bit ΣΔ A/D converters

We present a low-area and low-power implementation of the first anti-aliasing and decimation filter following an ultra-high speed 1-bit Sigma Delta A/D converter operating between 430-600Msps in a wireless transceiver. This filter is implemented as a sinc(4) polyphase structure that decimates by 16. Reduction in area is achieved by interleaving I and Q data and by implementing each phase of the filter as a hard-wired lookup table. The filter provides more than 150 dB of rejection in 400 kHz band and more than 87 dB of rejection in 4 MHz band making it suitable for multi-standard wireless applications. It is implemented in 90-nm digital CMOS process and the combined area for both I and Q channels is less than 3800 gates.