共 50 条
- [1] Simulation of Non-Uniform Wafer Geometry and Thin Film Residual Stress on Overlay Errors METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XXV, PT 1 AND PT 2, 2011, 7971
- [2] Overlay errors induced by metallic stress - Mechanism and solutions METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XVIII, PTS 1 AND 2, 2004, 5375 : 761 - 770
- [3] Investigation of residual stress in wafer level interconnect structures induced by wafer processing 56TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE 2006, VOL 1 AND 2, PROCEEDINGS, 2006, : 344 - +
- [4] Monitoring Process-Induced Overlay Errors through High-Resolution Wafer Geometry Measurements METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XXVIII, 2014, 9050
- [5] THE BASIC RELATIONSHIP BETWEEN MACHINING INDUCED RESIDUAL STRESS PROFILES AND FATIGUE LIFE MSEC 2008: PROCEEDINGS OF THE ASME INTERNATIONAL MANUFACTURING SCIENCE AND ENGINEERING CONFERENCE 2008, VOL 2, 2009, : 103 - 107
- [6] Model-based correction for local stress-induced overlay errors OPTICAL MICROLITHOGRAPHY XXXI, 2018, 10587
- [7] Residual stress in PVD coatings - Relationship between stress and texture HIGH TEMPERATURE MATERIAL PROCESSES, 1998, 2 (03): : 391 - 399
- [8] Study on the relationship between applied stress, residual strain and electrical resistance of shape memory alloys NiTi Gongneng Cailiao/Journal of Functional Materials, 1998, 29 (02): : 161 - 164