Delay-power product simulation results for one-hot residue number system arithmetic circuits

被引：0
|
作者：
Chren, WA
Brogdon, CH
Andrevska, D
机构：
来源：
PROCEEDINGS OF THE 39TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III | 1996年
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TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We present Spice simulations which verify previous analytical estimates of the delay-power product of One-Hot Residue adders and multipliers. These simulations show greater than a 50% reduction in the product below binary adders and an order of magnitude reduction for multipliers. Analytical models are derived from these results. They can be used to predict performance for larger moduli.
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页码：544 / 547
页数：4
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