A Study of SiCN Cap Process Resultant Plasma Induced Damage in 40nm technology node

Plasma processes are widely used in the manufacturing of Very Large Scale Integration (VLSl) devices for dry etching and dielectric film deposition. Damage induced by plasma becomes inevitable and can potentially break the gate dielectric bonds and increase gate dielectric leakage current, which would give rise to transistor threshold voltage and lead to device failure. In this study, a gate oxide leakage failure dominantly in wafer center was observed in 40nm technology nodes and it is believed that this failure is related to SiCN Cu interconnect cap film deposition. To investigate the failure mechanisms, SiCN films were deposited with two different types of commercial tools. The SiCN film surface charge results showed that the charge value in wafer center was obviously higher than that in wafer edge. The plasma density measurement result also revealed that plasma density in the chamber center is higher than that of wafer edge. Plasma induced damage (PID) test data indicated that the deposition initial step, the NH3 pretreatment stage, was not the key factor, but the main step of SiCN film deposition played the important role in the device damage. By adjusting the main deposition step, the film surface charge value and the charge uniformity were much improved, which led to a solution to the wafer central PID issue at 40nm device.