Design of low phase noise and low power modified current-reused VCOs for 10 GHz applications

In this paper, we present low phase noise and low power of the modified current-reused VCOs for 10 GHz application. Three chips are implemented by the standard 0.18 mu m CMOS process. The improvement of the VCOs' three chips is described step by step. The traditional current-reused circuit with a wide tuning range of 17.2% is presented in the first chip. It has a phase noise-118 dBc/Hz at 1 MHz offset and 5 mW core power dissipation with a voltage supply under 1.5 V. The performance of FOM is as high as -191.8 dBc/Hz. Extra NMOS cross-coupled pairs inside the traditional current-reused circuit in the second chip is proposed to speed up the oscillation and stability. The phase noise is -106.19 dBc/Hz and the core power dissipation is 3 mW with a voltage supply under 1.5 V. For the third chip, two dc level shifters are adopted to improve the symmetry of the output signal and to decrease noise interference. The phase noise and core power are -106.9 dBc/Hz and 2.88 mW, respectively. It also has a high performance of FOM with -182.4 dBc/Hz. (C) 2012 Elsevier Ltd. All rights reserved.