A Novel AES-256 Implementation on FPGA using Co-processor based Architecture

被引:0
|
作者
Sau, Suman [1 ]
Paul, Rourab [2 ]
Biswas, Tanmay [1 ]
Chakrabarti, Amlan [1 ]
机构
[1] Univ Calcutta, AK Choudhury Sch Informat Technol, Kolkata, India
[2] Univ Calcutta, Dept Elect Sci, Kolkata, India
关键词
FPGA; AES; Security; XPS; FSL; Crypto co-processor;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Efficient hardware architecture for cryptographic algorithms are of utmost need for implementing secured data communication in embedded applications. The hardware implementation of the algorithms though provides less flexibility, but are faster and requires less resource as compared to the software implementation, and hence ideally suited for target specific embedded systems. Though, there exist quite a few research works that propose hardware design for implementing cryptographic algorithm on various hardware platforms like application specific integrated circuit (ASIC), field programmable gate array (FPGA) and micro-controllers, still there lies the need of better hardware design in terms of larger key values, higher throughput and less resource utilization. In this paper we present a co-processor based architectural design and the related embedded system implementation for the encryption standard algorithm (AES-256). Our proposed design is an FPGA based architecture, having a custom crypto co-processor for executing the encryption and the decryption operations, which also communicates with the main processor core with the high speed fast simplex link (FSL) as and when required. The proposed design allows our hardware to perform multi-tasking, which is performed by a dedicated crypto co-processor executing the crypto functions and the main processor core executing the other application tasks. So in a sense our co-processor based design is novel, as it provides a high speed hardware execution of the crypto functions as well as provides the flexibility of executing the other application tasks on the main processor core of the system. Our implementation worked successfully for encryption and decryption of data over an Ethernet network. To the best of our knowledge, the co-processor based architectural design of AES-256 using FPGA devices, is first of its kind. Our design proves to be efficient in terms of throughput and resource utilization in comparison with the related research works.
引用
收藏
页码:632 / 638
页数:7
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