共 50 条
- [1] FPGA Implementation of AES Co-processor in Counter Mode INFORMATION PROCESSING AND MANAGEMENT, 2010, 70 : 491 - +
- [2] An FPGA Co-Processor Implementation of Homomorphic Encryption 2014 IEEE HIGH PERFORMANCE EXTREME COMPUTING CONFERENCE (HPEC), 2014,
- [3] TIME OPTIMIZATION OF AES-256 HARDWARE IMPLEMENTATION 2014 22ND TELECOMMUNICATIONS FORUM TELFOR (TELFOR), 2014, : 427 - 430
- [4] A novel reconfigurable co-processor architecture TENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 1997, : 370 - 375
- [5] DESIGN AND IMPLEMENTATION OF ROUGH SET CO-PROCESSOR ON FPGA INTERNATIONAL JOURNAL OF INNOVATIVE COMPUTING INFORMATION AND CONTROL, 2015, 11 (02): : 641 - 656
- [6] Power Analysis Resistant AES Crypto Engine Design and FPGA Implementation for a Network Security Co-processor 2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2009, : 933 - 936
- [7] A host/co-processor FPGA-based architecture for fast image processing IDAACS 2007: PROCEEDINGS OF THE 4TH IEEE WORKSHOP ON INTELLIGENT DATA ACQUISITION AND ADVANCED COMPUTING SYSTEMS: TECHNOLOGY AND APPLICATIONS, 2007, : 373 - +
- [8] FPGA IMPLEMENTATION AND INTEGRATION OF A RECONFIGURABLE CAN-BASED CO-PROCESSOR TO THE COFFEE RISC PROCESSOR 2016 2ND IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS), 2016,
- [9] Single-chip FPGA implementation of a cryptographic co-processor 2004 IEEE INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY, PROCEEDINGS, 2004, : 279 - 285
- [10] A Low Cost Advanced Encryption Standard (AES) Co-Processor Implementation JOURNAL OF COMPUTER SCIENCE & TECHNOLOGY, 2008, 8 (01): : 8 - 14