A non-zero clock skew scheduling algorithm for high speed clock distribution network

被引：0

作者：

Maaz, MB ^{[1
]}

Bayoumi, MA ^{[1
]}

机构：

[1] Univ SW Louisiana, Ctr Adv Comp Studies, Lafayette, LA 70504 USA

来源：

ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 6: CIRCUITS ANALYSIS, DESIGN METHODS, AND APPLICATIONS | 1999年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we present a novel algorithm for scheduling clock skews in a synchronous digital circuits to optimize performance. The new algorithm is based on inclusively matching allowable clock skews intervals of all local data path in the circuit in order to determine the proper global skew ranges. This algorithm will lead to minimizing the clock period as well as obtaining a list of scheduled skews to be inserted in the clock network. These scheduled skews are then used to obtain a delay model for all branches of the clock distribution network tree. The delay values ensure the proper synchronization of data and eliminate any potential race condition in the circuit. The new algorithm has been tested and found to be a good approach toward reducing the clock period compared with zero intentional skew clocking.

引用

页码：382 / 385

页数：4

共 50 条

[1] A non-zero clock skew scheduling algorithm for high speed clock distribution network
Maaz, MB
Bayoumi, MA
42ND MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS, VOLS 1 AND 2, 1999, : 800 - 803
[2] Clock period minimization of non-zero clock skew circuits
Huang, SH
Nieh, YT
ICCAD-2003: IEEE/ACM DIGEST OF TECHNICAL PAPERS, 2003, : 809 - 812
[3] Demonstration of speed enhancements on an industrial circuit through application of non-zero clock skew scheduling
Velenis, D
Tang, KT
Kourtev, IS
Adler, V
Baez, F
Friedman, EG
ICECS 2001: 8TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-III, CONFERENCE PROCEEDINGS, 2001, : 1021 - 1025
[4] Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations
Josè Luis Neves
Eby G. Friedman
Journal of VLSI signal processing systems for signal, image and video technology, 1997, 16 : 149 - 161
[5] Buffered clock tree synthesis with non-zero clock skew scheduling for increased tolerance to process parameter variations
Neves, JL
Friedman, EG
JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 1997, 16 (2-3): : 149 - 161
[6] Zero skew differential clock distribution network
Zarrabi, Houman
Saaied, Haydar
Al-Khalili, A. J.
Savaria, Yvon
2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, 2006, : 2077 - 2080
[7] Clock skew analysis in optical clock distribution network
Tosik, Grzegorz
Abramowicz, Filip
Lisik, Zbigniew
Gaffiot, Frederic
2007 PROCEEDINGS OF THE 9TH INTERNATIONAL CONFERENCE ON THE EXPERIENCE OF DESIGNING AND APPLICATION OF CAD SYSTEMS IN MICROELECTRONICS, 2007, : 422 - +
[8] A global minimum clock distribution network augmentation algorithm for guaranteed clock skew yield
Liu, Bao
Kahng, Andrew B.
Xu, Xu
Hu, Jiang
Venkataraman, Ganesh
PROCEEDINGS OF THE ASP-DAC 2007, 2007, : 25 - +
[9] AN EXACT ZERO-SKEW CLOCK ROUTING ALGORITHM
TSAY, RS
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1993, 12 (02) : 242 - 249
[10] Multi-Domain Clock Skew Scheduling-Aware Register Placement to Optimize Clock Distribution Network
MohammadZadeh, Naser
Mirsaeedi, Minoo
Jahanian, Ali
Zamani, Morteza Saheb
DATE: 2009 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, VOLS 1-3, 2009, : 833 - +

← 1 2 3 4 5 →