Framework for neural network hardware implementation

Artificial neural networks (ANN) are widely used in solving problems like image processing, data mining, or classification. Hardware accelerators are used for increasing the performance and efficiency of neural networks. An option for implementing such an accelerator is the usage of an FPGA-based system, although developing neural networks for FPGAs is very time-consuming and requires hardware design knowledge to do it. This problem tried to be solved by creating a framework that should speed up the design process. At the same time, there is an overall outlook on some efficiency optimization and speed-up options as well. The framework is written in Python and generates a C++ code whit HLS directive. This code can be compiled by Vivado HLS into a hardware descriptive language and packaged as an IP. The Vivado tool can generate a bit file that can be uploaded onto the FPGA device. Among other things, the paper presents a comparison of different approximations of nonlinear transformations (basis functions and activation functions) in terms of accuracy, required resource, and delay needed for evaluating the transformation. The generated neural network module was integrated into a system that was developed by the authors. Using that system, the neural network module was tested and compared to the models implemented in Python.