A Hardware Efficient Implementation of Chroma Interpolator for H.264 Encoders

被引：0

作者：

Wang, Teng ^{[1
]}

Zhao, Lei ^{[1
]}

Hu, Ziyi ^{[1
]}

Xie, Zheng ^{[1
]}

Wang, Xin'an ^{[1
]}

机构：

[1] Peking Univ, Shenzhen Grad Sch, Key Lab Integrated Microsyst, Shenzhen 518055, Peoples R China

来源：

2011 INTERNATIONAL CONFERENCE OF ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC) | 2011年

关键词：

Arithmetic Decomposation; Chroma Interpolator; Hardware Resue; H.264; STANDARD;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, an implementation of the chroma interpolator with great hardware reuse and no multipliers for H. 264 encoders is proposed. First, the characteristic of the chroma interpolation is analyzed to obtain an optimized decomposition scheme, with which the chroma interpolation can be realized with arithmetic elements which are comprised of only adders. The design was prototyped within a Xilinx Virtex6 FPGA at 245 MHz. The design was also synthesized with SMIC 130ns CMOS technology at 200 MHz, which can support a real-time HDTV application.

引用

页数：2

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