High-Accuracy Current Memory in HV CMOS Technology

This brief describes an improved current memory circuit aimed at circumventing problems inherent in using a high-voltage double-diffused MOS (DMOS) with CMOS technology. In addition to dealing with the excessive output conductance of a simple cell with cascoding in the familiar way, the circuit addresses the significant drain-gate feedthrough seen in such technologies. A replica bias scheme ensures that the g(m) of the memory device remains substantially constant notwithstanding the signal current level variations, leading to improved control over charge injection errors. The topology may also be used in conventional small geometry CMOS technology.