L2 cache/controller runs 66-MHz PowerPC

被引：0
|
作者：
不详
机构：
来源：
COMPUTER DESIGN | 1996年 / 35卷 / 01期
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
引用
收藏
页码：126 / 129
页数：4
相关论文
共 50 条
  • [1] 250-MHz 5-W PowerPC microprocessor with on-chip L2 cache controller
    Somerset Design Cent, Austin, United States
    IEEE J Solid State Circuits, 11 (1635-1649):
  • [2] A 250-MHz 5-W PowerPC microprocessor with on-chip L2 cache controller
    Gerosa, G
    Alexander, M
    Alvarez, J
    Croxton, C
    DAddeo, M
    Kennedy, AR
    Nicoletta, C
    Nissen, JP
    Philip, R
    Reed, P
    Sanchez, H
    Taylor, SA
    Burgess, B
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (11) : 1635 - 1649
  • [3] GAAS/CMOS CACHE CHIP SET POWERS 66-MHZ CPUS
    BURSKY, D
    ELECTRONIC DESIGN, 1993, 41 (11) : 43 - &
  • [4] A 250MHz 5W RISC microprocessor with on-chip L2 cache controller
    Reed, P
    Alexander, M
    Alvarez, J
    Brauer, M
    Chao, CC
    Croxton, C
    Eisen, L
    Le, T
    Ngo, T
    Nicoletta, C
    Sanchez, H
    Taylor, S
    Vanderschaaf, N
    Gerosa, G
    1997 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE - DIGEST OF TECHNICAL PAPERS, 1997, 40 : 412 - 413
  • [5] Design of Controller for L2 Cache Mapped in Tezzaron Stacked DRAM
    Tshibangu, Nyunyi M.
    Franzon, Paul D.
    Rotenberg, Eric
    Davis, William R.
    2013 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC), 2013,
  • [6] Compressed L1 Data Cache and L2 Cache in GPGPUs
    Atoofian, Ehsan
    2016 IEEE 27TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP), 2016, : 1 - 8
  • [7] Adaptive L2 cache for chip multiprocessors
    Benitez, Domingo
    Moure, Juan C.
    Rexachs, Dolores I.
    Luque, Emilio
    EURO-PAR 2007 WORKSHOPS: PARALLEL PROCESSING, 2008, 4854 : 28 - +
  • [8] Location cache: A low-power L2 cache system
    Min, R
    Jone, WB
    Hu, YM
    ISLPED '04: PROCEEDINGS OF THE 2004 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2004, : 120 - 125
  • [9] Exploiting Replicated Cache Blocks to Reduce L2 Cache Leakage in CMPs
    Kim, Hyunhee
    Ahn, Jung Ho
    Kim, Jihong
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2013, 21 (10) : 1863 - 1877
  • [10] An efficient racetrack memory for L2 cache in GPGPUs
    Atoofian, Ehsan
    Saghir, Ahsan
    COMPUTER SYSTEMS SCIENCE AND ENGINEERING, 2017, 32 (06): : 461 - 471
12345