An FPGA-accelerated Doppler Parameters Estimation Engine for Real-time Synthetic Aperture Radar Imaging System

被引:1
|
作者
Li, Bingyi [1 ,2 ]
Wang, Ying [3 ]
Fang, Linlin [1 ,2 ]
Xie, Yizhuang [1 ,2 ]
Chen, He [1 ,2 ]
Chen, Liang [1 ,2 ]
机构
[1] Beijing Inst Technol, Sch Informat & Elect, Radar Res Lab, Beijing, Peoples R China
[2] Beijing Key Lab Embedded Real Time Informat Proc, Beijing, Peoples R China
[3] Shanghai Acad Spaceflight Technol, Beijing, Peoples R China
关键词
SAR; Doppler parameter; FPGA accelerator;
D O I
10.1109/ICISCE.2017.45
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, we demonstrate an achievable implementation of Doppler parameters estimation engine. Taking advantage of FPGA, a highly parallelized and reconfigurable structure with a unified calculation is adopted. We build a prototype using single off-the-shelf Xilinx XC6VSX315T FPGA to verify the proposed method in a 16384 X 16384 SAR imaging process. The experiment result can achieve more than 20x time speedups over CPU-based solution, and the FPGA hardware resources can be balanced.
引用
收藏
页码:169 / 171
页数:3
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