LOW POWER DIGITAL DECIMATION FILTER FOR RF WIRELESS COMMUNICATIONS

In this paper, we present a unique low power decimation filter architecture for RF wireless applications. To implement the low power decimation filter, we considered low power design techniques such as multi-rate, multi-stage signal processing, proper selection of decimation factor, one multiplier realization of 1/3-band filters, and poly-phase 1/2band filters. We have designed three conventional decimation filter architectures using a single-stage FIR filter, a three-stage FIR filter, and a three-stage half-band FIR filter. Compared to the 55-tap comb-FIR filter architecture, the proposed decimation filter has only 13 taps, and requires 76% less hardware and consumes 64% less power.