NEMS Switches for Ultra-Low-Power Digital Logic: Challenges and Opportunities

被引:0
|
作者
Munoz-Gamarra, J. L. [1 ]
Poulain, C. [1 ]
Ludurczak, W. [1 ]
Hentz, S. [1 ]
Hutin, L. [1 ]
机构
[1] Commissariat Energie Atom & Energies Alternat, CMOS Integrat Lab, 17 Rue Martyrs, F-38054 Grenoble, France
来源
2016 IEEE 16TH INTERNATIONAL CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO) | 2016年
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中图分类号
TB3 [工程材料学];
学科分类号
0805 ; 080502 ;
摘要
A renewed interest in mechanical computing has emerged in Microelectronics in the last years as a solution to the increasing static power density of CMOS technologies as they are scaled down. Nano-electromechanical (NEMS) switches can be used as the new digital logic building block, leveraging the benefits of ideally zero OFF state current. Current efforts are underway aiming at demonstrating low operating voltages and potential for scalability. On the other hand they still present some drawbacks that need to be addressed: slow response and insufficient contact reliability. In this work an overview of the fundamental working principles, state-of-the-art and main challenges will be assessed for standalone N/MEMS logic circuits. Additionally, an alternative hybrid CMOS/NEMS route is proposed, useful for some particular applications.
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收藏
页码:871 / 874
页数:4
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