0.35μm, 30V Fully Isolated and Low-Ron nLDMOS for DC-DC Applications

被引：0

作者：

Lee, Kyungho ^{[1
]}

Jeon, Haeung ^{[1
]}

Cho, Byunghee ^{[1
]}

Cho, Joonhee ^{[1
]}

Pang, Yon-Sup ^{[1
]}

Moon, Jinwoo ^{[1
]}

Kwon, Susanna ^{[1
]}

Hebert, Francois ^{[1
]}

Lee, Junghwan ^{[1
]}

Lee, Taejong ^{[1
]}

机构：

[1] Magnachip Semicond, Corp Engn Div, Cheongju 361728, Chungcheongbuk, South Korea

来源：

2013 25TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD) | 2013年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we present a new approach to integrate in a 0.35 mu m BCD technology, low Ron LDMOS power transistors with highly competitive Specific Resistance figure of merit (Rsp, defined as Ron*Area). The LDMOS are fully isolated in order to support applications which may bias the source/drain electrodes below the substrate potential, which is critical for devices used in high-current, high- frequency switching applications. The new devices are suitable for high-efficiency DC-DC converter products with operating voltage of up to 30V, such as mobile PMICs. For maximum performance, two different extended-drain LDMOS structures have been developed to cover the entire operating voltage range: for 16V and below, a planar-gate structure is used and for 20V and above, a non-planar "offset-LOCOS" gate is used for 20V and above.

引用

页码：163 / 166

页数：4

共 22 条

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