Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance

Timing-error detection and recovery circuits are implemented in a 65nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (V-CC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous EDS designs while lowering clock energy and removing datapath metastability. Error-recovery circuits replay failing instructions at lower clock frequency to guarantee correct functionality. Relative to conventional circuits, silicon measurements indicate that resilient circuits enable either 25 to 32% throughput gain at equal V-CC or at least 17% V-CC reduction at equal throughput, resulting in 31 to 37% total power reduction.