Effect of Ashing Conditions and Optimization of Nano Process Integration in Copper/Porous Low-k Nano-Interconnects

We report the optimization of ashing conditions and the process integration of a chemical vapor deposition (CVD) ultra low-k (k=2.2) organosilicate (OSG) dielectric in a top hard mask damascene structure. The N-2/H-2 ash showed the lowest resistance-capacitance (RC) product and a dual top hard mask approach for dual damascene processing was built, using 200 nm SiC/50 nm SiO2 as the hard mask. This CVD low-k material had no low-k voiding, unlike other spin-on dielectric (SOD) low-k materials. The presence of the densified layer around the trench during the ashing process could improve the precursor penetration during the CVD barrier metal deposition process.