Implementation of ESD protection in SOI technology: A simulation study

Implementation of ESD protection circuits in SOI technology is well-known to be challenging due to inherent properties of SOI devices. While in comparison to bulk-Si SOI has excellent speed and power consumption features, its current handling capabilities are less impressive. This is due to thin-film current conduction properties and potential heat trapping in the thin film on top of a poor heat conductor (oxide). Design of ESD circuits in SOI is further complicated by the presence of the floating body effect, not adequately considered by conventional circuit simulators. In this work we present results of mixed-mode circuit-device simulation of ESD properties of SOI devices, including film thickness effects, heating during HBM and estimated failure current levels (It2).