VLSI implementations of low-power leading-one detector circuits

被引：14
|
作者：
Abed, Khalid H. [1 ]
Siferd, Raymond E. [2 ]
机构：
[1] Jackson State Univ, Dept Comp Engn, Jackson, MS 39217 USA
[2] Wright State Univ, Dept Elect Engn, Dayton, OH 45435 USA
来源：
PROCEEDINGS OF THE IEEE SOUTHEASTCON 2006 | 2006年
关键词：
D O I：
10.1109/second.2006.1629364
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
This paper presents two approaches to design leading-one detector (LOD) circuits, which locate the leading-one position in a binary word. The first approach provides fast leading-one detectors (LODs), and the second emphasizes the design of novel hardware-efficient and low-power LODs. Each approach is used to obtain 0.6 mu m CMOS VLSI implementations of 16-, 32-, and 64-bit LOD circuits. Simulations of the 16-, 32-, and 64-bit fast LODs run at 310, 265, and 215 MHz, respectively. The 16-, 32-,and 64-bit low-power LODs consume 14.85, 44.70, and 61.67 milliwatts, respectively while operating at VDD equal to 5 volts and their maximum speed.
引用
收藏
页码：279 / 284
页数：6
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