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- [1] Power-Aware Mapping for 3D-NoC Designs using Genetic Algorithms 9TH INTERNATIONAL CONFERENCE ON FUTURE NETWORKS AND COMMUNICATIONS (FNC'14) / THE 11TH INTERNATIONAL CONFERENCE ON MOBILE SYSTEMS AND PERVASIVE COMPUTING (MOBISPC'14) / AFFILIATED WORKSHOPS, 2014, 34 : 538 - 543
- [3] A Comparative Analysis of Fault Tolerance Methods in 3D-NoC 2021 SIXTH INTERNATIONAL CONFERENCE ON WIRELESS COMMUNICATIONS, SIGNAL PROCESSING AND NETWORKING (WISPNET), 2021, : 171 - 177
- [4] Three-Dimensional Packaging Structure for 3D-NoC 2013 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS), 2013, : 72 - 75
- [6] System level Modeling and Verification for Routers of 3D-NoC Based on System C PROCEEDINGS OF THE 2015 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2015, : 479 - 482
- [7] Fault-Tolerant Circular Routing Algorithm for 3D-NoC 2014 INTERNATIONAL CONGRESS ON TECHNOLOGY, COMMUNICATION AND KNOWLEDGE (ICTCK), 2014,
- [8] Memory-Centric Fusion-based CNN Accelerator with 3D-NoC and 3D-DRAM 2022 19TH INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2022, : 169 - 170
- [9] CoBRA: Low Cost Compensation of TSV failures in 3D-NoC 2016 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFT), 2016, : 115 - 120