A Hardware-Efficient Approximate Multiplier Combining Inexact Same-weight N:2 Compressors and Remapping Logic with Error Recovery

被引：1

作者：

Duan, Renrui ^{[1
]}

Zhang, Mingtao ^{[1
]}

Guo, Yi ^{[2
]}

Nishizawa, Shinichi ^{[1
]}

Kimura, Shinji ^{[1
]}

机构：

[1] Waseda Univ, Grad Sch Informat Prod & Syst, Kitakyushu, Fukuoka, Japan

[2] Yunnan Univ, Sch Informat Sci & Engn, Kunming, Yunnan, Peoples R China

来源：

2023 IEEE 36TH INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE, SOCC | 2023年

关键词：

approximate computing; approximate multiplier; compressor; error recovery; DESIGN;

D O I：

10.1109/SOCC58585.2023.10257018

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Approximate computing can trade accuracy for smaller power, delay, and area. So, approximate computing is hardware-efficient for fault-tolerant applications which do not require full precision, such as image processing and machine learning. This paper proposes same-weight N:2 compressors based on the probability analysis, and construct approximate multipliers combining proposed N:2 compressors, remapping logic and constant-truncation with its error recovery circuit. Evaluation results using commercial 65 nm process library show that proposed 8x8 multiplier has good hardware-accuracy tradeoff. It reduces the power by 39%, the delay by 17%, the area by 34% and the power-delay-area-product (PDAP) by 67% with an MRED of 1.27% when compared to the exact multiplier. The proposed methods show the better PDAP compared with other approximate multipliers with almost the same MRED.

引用

页码：250 / 255

页数：6