Scalable Multi-Stage CMOS OTAs With a Wide CL-Drivability Range Using Low-Frequency Zeros

work introduces a multi-stage CMOS OTA design technique that allows cascading identical gain stages (for arbitrarily scalable high DC gain) while driving an ultra-wide range of capacitive loads (CLs). At the heart of the proposed design is a new frequency compensation technique (FCT) that relies on low-frequency left-half-plane zeros to allow the proposed OTA to operate for a desired closed-loop behavior. In this work, classical gain-stages (i.e., differential pair and common source transistors) are used to design fully-differential 2-, 3-, 4-and 5-stage CMOS OTAs. The proposed 2-to-4-stage designs have been fabricated in TSMC 65 nm CMOS process and the measurement results show that the 2-stage OTA is achieving a DC gain of 50 dB with a CL-drivability ratio (i.e., C-L,C-max/C-L,C-min) of 10,000x, the 3-stage OTA is achieving a DC gain of 70 dB with a C-L-drivability of 1,000,000x, and the 4-stage OTA is achieving a DC gain of 90 dB with a CL-drivability of 1,000,000x. This is a 10-to-1000-time improvement in the state-of-the-art, as the highest C-L-drivability reported to date is 1000x. Accordingly, the proposed OTAs can cover a wider range of applications than any other reported works.