Exact and approximate multiplications for signal processing applications

Approximate computing is an emerging technique that can be used for developing power, area and delay efficient circuits at the cost of loss of accuracy. This paper investigates the possibility of efficient exact multipliers through the use of improved compressors and counters and thereafter deriving approximate multiplier structures to achieve a higher percentage of logic optimization at the expense of the lowest possible error. NAND gate based array structure with reduced complexity is used for generating the partial products for both the exact and approximate multipliers. Two variants of the efficient exact multiplier are proposed. The proposed exact multiplier EM-1 is area and power efficient, whereas EM-2 is delay and energy efficient. Two variants of 4:2 compressors are introduced for developing approximate multipliers. The proposed multipliers excel most of the state-of-the-art existing multipliers in terms of the important performance metrics. The proposed exact and approximate multiplier designs are employed for developing ECG denoising FIR filter for the elimination of power line interference and the corresponding performance improvement is illustrated. Cadence RTL compiler v11.10 with GPDK 45 nm standard cell library is used for the synthesis. The simulation of all the multipliers is done by running a test bench program using modelsim.