FlexKA: A Flexible Karatsuba Multiplier Hardware Architecture for Variable-Sized Large Integers

被引:2
|
作者
Kang, Byeongmin [1 ]
Cho, Hyungmin [1 ]
机构
[1] Sungkyunkwan Univ, Dept Comp Sci & Engn, Suwon 16419, South Korea
关键词
Hardware; Signal processing algorithms; Algorithms; Software algorithms; Memory modules; Software; Memory management; Multiplying circuits; field programmable gate arrays; DESIGN;
D O I
10.1109/ACCESS.2023.3282646
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
The Karatsuba algorithm is an effective way to accelerate large integer multiplications through recursive function calls. However, existing hardware implementations of Karatsuba multipliers are limited to fixed operand sizes. To enable their application in diverse domains, including homomorphic encryption with varying multiplicative depths, it is necessary to support variable operand sizes. In this paper, we propose a novel Karatsuba multiplier design, named FlexKA, which supports variable operand sizes through a state machine that manages the dynamic call states of the operation. We evaluate FlexKA on the Xilinx ZynqMP FPGA and demonstrate that it supports variable operand sizes up to 256K bits, achieving a 9.2x speedup compared to a highly-optimized software library running on a CPU. Our results show that FlexKA is an efficient and effective solution for large integer multiplications with flexible operand sizes in hardware.
引用
收藏
页码:55212 / 55222
页数:11
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