Low power capacitive-to-digital converter based on incremental delta-sigma modulator

被引：1
|
作者：
Wei, Rongshan [1 ]
Wei, Cong [1 ]
Huang, Lijie [1 ]
Huang, Gongxing [1 ]
Wang, Renping [1 ]
Hu, Wei [1 ]
机构：
[1] Fuzhou Univ, Sch Phys & Informat Engn, Fuzhou 350116, Peoples R China
来源：
MICROELECTRONICS JOURNAL | 2023年 / 142卷
基金：
中国国家自然科学基金;
关键词：
Capacitive-to-digital; Current-starved OTA; Delta-sigma; Low power; CMOS;
D O I：
10.1016/j.mejo.2023.106025
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents a low-power capacitive-to-digital converter (CDC) based on incremental delta-sigma modulator. It utilizes a zoom-in sensing capacitor that is insensitive to parasitic capacitance, improving the capacitance resolution. The use of a high-gain, PVT-robust current-starved OTA and a dynamic bias comparator enhances the efficiency of the system. An ultra-low-power bias circuit is integrated into the system, further improving integration and efficiency. The proposed CDC is fabricated using a 180 nm CMOS process. Operating at a 1.2 V supply voltage and a 250 kHz sampling frequency. With a measurement time of 0.8 ms, the capacitance resolution is 107.6 aF, and the power consumption is 10.27 mu W. The figure-of-merits (FoM) is 2.06 pJ/step.
引用
收藏
页数：6
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