Verification of 1 MHz Multisampling Disturbance Compensation Deadbeat Control for Megawatt-Level Grid-Tied Multi-level Inverter using Hardware-in-the-loop Controller

The impact on the stability of power systems is also increasing with the rapid spread of distributed power-supply systems. Consequently, the performance requirements for grid-tied inverters are increasing. However, MW-level grid-connected inverters have limited carrier frequency. This paper proposes a disturbance compensation deadbeat control with a 1 MHz multi-sampling method that can respond to changes in state variables between carrier intervals by increasing the sampling frequency even at low carrier frequencies. An FPGA-based hardware controller is used to implement all control calculations in the FPGA circuit. In addition, controller hardware-in-the-loop (C-HIL) is used to verify the control performance solving the difficulty of experimental verification in a megawatt-class grid-tied inverter. The control system can be verified using the controller used in an actual system. The effectiveness of the proposed method is demonstrated by verifying the control system with the C-HIL platform, and its superior characteristics are confirmed.