A 94.6dB-SNDR 50kHz-BW 1-1-1 MASH ADC Using OTA-FIA Based Integrators

被引：4
|
作者：
Hao, Xirui [1 ]
Chen, Junsheng [1 ]
Meng, Lingxin [1 ]
Zhao, Menglian [1 ]
Tan, Zhichao [1 ]
机构：
[1] Zhejiang Univ, Coll Informat Sci & Elect Engn, Hangzhou 310027, Zhejiang, Peoples R China
来源：
2023 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS | 2023年
基金：
国家重点研发计划; 中国国家自然科学基金;
关键词：
Delta-sigma Modulator (DSM); Multistage noise shaping (MASH); dynamic amplifiers; floating inverter amplifiers (FIAs); NOISE-SHAPING SAR;
D O I：
10.1109/ISCAS46773.2023.10181887
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
This paper presents a novel two-stage amplifier, which cascades a duty-cycled inverter-based OTA and a floating-inverter amplifier (FIA). The proposed OTA-FIA can achieve 72.0dB gain under a 1.2V supply, whose output swing is 420mV. Additionally, it exhibits intrinsic loop stability without compensation and reduces thermal noise during integration. The proposed OTA-FIA is adopted in a low distortion 1-1-1 MASH structure to obtain high resolution. Simulated in a 55 nm CMOS process, the proposed ADC can achieve an SNDR of 94.6dB with a bandwidth of 50kHz. It consumes 363.8 mu W from a 1.2V supply at a 5MS/s sampling frequency, resulting in a 176.0dB SNDR-based Schreier FoM.
引用
收藏
页数：4
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