Double-sided Row Hammer Effect in Sub-20 nm DRAM: Physical Mechanism, Key Features and Mitigation

被引：11

作者：

Zhou, Longda ^{[1
,2
,3
]}

Li, Jie ^{[1
,2
,3
]}

Qiao, Zheng ^{[1
,2
,3
]}

Ren, Pengpeng ^{[1
,2
,3
]}

Sun, Zixuan ^{[4
]}

Wang, Jianping ^{[5
]}

Wu, Blacksmith ^{[5
]}

Ji, Zhigang ^{[1
,2
,3
,6
]}

Wang, Runsheng ^{[4
,6
]}

Cao, Kanyu ^{[5
]}

Huang, Ru ^{[4
]}

机构：

[1] Shanghai Jiao Tong Univ, Natl Key Lab Sci & Technol Micro Nano Fabricat, Shanghai, Peoples R China

[2] Peking Univ, Beijing, Peoples R China

[3] Shanghai Jiao Tong Univ, Dept Micro Nano Elect, SEIEE, Shanghai 200240, Peoples R China

[4] Peking Univ, Sch Integrated Circuit, Beijing 100871, Peoples R China

[5] ChangXin Memory Technol, Hefei 230601, Peoples R China

[6] Beijing Superstring Acad Memory Technol, Beijing 100176, Peoples R China

来源：

2023 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, IRPS | 2023年

基金：

中国国家自然科学基金;

关键词：

Capacitive crosstalk; DRAM; process dependence; row hammer effect; trap-assisted electron migration;

D O I：

10.1109/IRPS48203.2023.10117677

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

The double-sided row hammer (rh) effect at the silicon level for sub-20 nm dynamic random access memory (DRAM) is systematically investigated for the first time. Based on 3D TCAD simulation, the impacts of capacitive crosstalk and electron migration are investigated. The latter with trap assistance is found the dominant mechanism behind the enhancement of 1 failure and the alleviation of 0 failure for double-sided rh. Moreover, rh dependences on data pattern, timing parameters and technology nodes are compared under different rh conditions. A trade-off of retention time (tret) between 1 failure and 0 failure should be considered when suppressing the double-sided rh effect. With the co-optimization of key process parameters, tret for double-sided rh-induced 1 failure can be improved by 220 times.

引用

页数：10

共 5 条

[1] Understanding the Competitive Interaction in Leakage Mechanisms for Effective Row Hammer Mitigation in Sub-20 nm DRAM
Li, Jie
Zhou, Longda
Ye, Sheng
Qiao, Zheng
Ji, Zhigang
IEEE ELECTRON DEVICE LETTERS, 2024, 45 (01) : 40 - 43
[2] Unveiling RowPress in Sub-20 nm DRAM Through Comparative Analysis With Row Hammer: From Leakage Mechanisms to Key Features
Zhou, Longda
Ye, Sheng
Wang, Runsheng
Ji, Zhigang
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2024, 71 (08) : 4677 - 4684
[3] Understanding the Physical Mechanism of RowPress at the Device-Level in Sub-20 nm DRAM
Zhou, Longda
Li, Jie
Ren, Pengpeng
Ye, Sheng
Wang, Da
Qiao, Zheng
Ji, Zhigang
2024 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, IRPS 2024, 2024,
[4] Row hammer-induced D0 failure improvement in sub-20 nm DRAM using an air gap
Yoon, Jiyeong
Yoon, Seokchan
Ahn, Jinho
Shin, Changhwan
SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2024, 39 (12)
[5] Suppression of Row Hammer Effect by Doping Profile Modification in Saddle-Fin Array Devices for Sub-30-nm DRAM Technology
Yang, Chia-Ming
Wei, Chen-Kang
Chang, Yu Jing
Wu, Tieh-Chiang
Chen, Hsiu-Pin
Lai, Chao-Sung
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2016, 16 (04) : 685 - 687

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