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- [3] Analysis and improvement of retention time of memorized state of metal-ferroelectric-insulator-semiconductor structure for ferroelectric gate FET memory JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 2001, 40 (4B): : 2923 - 2927
- [4] Analysis and improvement of retention time of memorized state of metal-ferroelectric-insulator-semiconductor structure for ferroelectric gate FET memory Takahashi, M., 2001, Japan Society of Applied Physics (40):
- [9] Modeling of temperature characteristics for metal-ferroelectric-insulator-semiconductor devices ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2007, : 1050 - 1053