Co-design of SLC/MLC FeFET-based highly error-tolerant low-power CiM and strong lottery ticket hypothesis-based algorithm

被引：1

作者：

Yamauchi, Kenshin ^{[1
]}

Yamada, Ayumu ^{[1
]}

Misawa, Naoko ^{[1
]}

Cho, Seong-Kun ^{[1
]}

Toprasertpong, Kasidit ^{[1
]}

Takagi, Shinichi ^{[1
]}

Matsui, Chihiro ^{[1
]}

Takeuchi, Ken ^{[1
]}

机构：

[1] Univ Tokyo, Dept Elect Engn & Informat Syst, Bunkyo, Tokyo 1234567, Japan

来源：

JAPANESE JOURNAL OF APPLIED PHYSICS | 2024年 / 63卷 / 04期

基金：

日本科学技术振兴机构;

关键词：

Computation-in-Memory; Strong Lottery Ticket Hypothesis; FeFET; INFERENCE; MEMORY;

D O I：

10.35848/1347-4065/ad2656

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

This study co-designs single-level cell (SLC) mask and multilevel cell (MLC) weight twin FeFET devices and a strong lottery ticket hypothesis (SLTH)-based neural network (NN) algorithm to achieve highly error-tolerant low-power Computation-in-Memory (CiM). The SLC mask FeFET masks or transfers the NN weight stored in the MLC weight FeFET, and the masked NN weight reduces the CiM power consumption. The proposed SLC mask FeFETs, which are trained, and MLC weight FeFETs, in which V TH are uniformly randomized, achieve 87% inference accuracy against 10-year data retention and read disturb. The SLC mask FeFETs show 86% inference accuracy even at 2000 endurance cycles. In addition, shared-bottom-select-gate (BSG) SLTH CiM and common-mask SLTH CiM for the NN convolutional layer are proposed to reduce the CiM area by sharing BSG and mask FeFET. Moreover, NN weight mapping schemes for SLTH CiM are proposed. The proposed mapping schemes show a tradeoff between inference accuracy and CiM area. One of the schemes reduces the CiM area by 45% with a 9.1% accuracy loss.

引用

页数：13