Functional Verification of a RISC-V Vector Accelerator

被引：1

作者：

Jimenez, Victor ^{[1
]}

Rodriguez, Mario ^{[1
]}

Dominguez, Marc ^{[1
]}

Sans, Josep ^{[1
]}

Diaz, Ivan ^{[1
]}

Valente, Luca ^{[1
]}

Guglielmi, Vito Luca ^{[1
]}

Quiroga, Josue V. V. ^{[1
]}

Genovese, R. Ignacio ^{[1
]}

Sonmez, Nehir ^{[1
]}

Palomar, Oscar ^{[1
]}

Moreto, Miquel ^{[1
]}

机构：

[1] Barcelona Supercomp Ctr, Comp Sci Dept, Validat Team, Barcelona 08034, Spain

来源：

IEEE DESIGN & TEST | 2023年 / 40卷 / 03期

基金：

欧盟地平线“2020”;

关键词：

Graphics processing units; Registers; Monitoring; Europe; Metadata; Context; Collaboration; verification; RISC-V; vector accelerator; UVM; coverage; random binary generation;

D O I：

10.1109/MDAT.2022.3226709

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Editor's notes: With the mounting interest in the public domain RISC-V instruction set architecture the complexity of verification on RISC-V CPUs is at the forefront. Every RISC-V implementation must ensure it fully complies with the programmer's manual, independent of the purpose of the program or the application. This article describes a reusable and extendable UVM environment to check the correctness of the executed instructions with a high degree of precision. -Vivek Chickermane, Cadence

引用

页码：36 / 44

页数：9

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