共 50 条
- [1] Novel Modeling Approach for Multi-walled CNT Bundle in Global VLSI Interconnects PROCEEDINGS OF THE 2012 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, DEVICES AND INTELLIGENT SYSTEMS (CODLS), 2012, : 476 - 479
- [2] A new level restoration circuit for multi-valued logic 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS, 2004, : 649 - 652
- [3] A Novel Design and Implementation of Multi-Valued Logic Arithmetic Full Adder circuit using CNTFET 2016 IEEE INTERNATIONAL CONFERENCE ON RECENT TRENDS IN ELECTRONICS, INFORMATION & COMMUNICATION TECHNOLOGY (RTEICT), 2016, : 563 - 568
- [4] Stability and delay analysis of multi-layered GNR and multi-walled CNT interconnects Journal of Computational Electronics, 2015, 14 : 611 - 618
- [6] A Model of Multi-Walled Carbon Nanotube Interconnects 2009 52ND IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2, 2009, : 987 - +
- [7] Symmetric ternary logic based multi-valued learning network Jisuanji Xuebao/Chinese Journal of Computers, 21 (06): : 553 - 559
- [8] Design of a Flash-based Circuit for Multi-valued Logic PROCEEDINGS OF THE GREAT LAKES SYMPOSIUM ON VLSI 2017 (GLSVLSI' 17), 2017, : 41 - 46
- [9] Propagation Delay Analysis for Bundled Multi-Walled CNT in Global VLSI Interconnects PROCEEDINGS OF THE SECOND INTERNATIONAL CONFERENCE ON SOFT COMPUTING FOR PROBLEM SOLVING (SOCPROS 2012), 2014, 236 : 1117 - 1126
- [10] Optimized Delay and Power Performances for Multi-walled CNT in Global VLSI Interconnects 2012 5TH INTERNATIONAL CONFERENCE ON COMPUTERS AND DEVICES FOR COMMUNICATION (CODEC), 2012,