A Low-Power Oscillatory Feature Extraction Unit for Implantable Neural Interfaces

被引：1

作者：

Yassin, Hoda ^{[1
]}

Akhoundi, Arash ^{[2
]}

Hasaneen, El-Sayed ^{[1
]}

Muratore, Dante G. ^{[2
]}

机构：

[1] Aswan Univ, Dept Elect Engn, Aswan, Egypt

[2] Delft Univ Technol, Dept Microelect, Delft, Netherlands

来源：

2023 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS | 2023年

关键词：

STIMULATION;

D O I：

10.1109/ISCAS46773.2023.10181914

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Power and area efficient on-chip feature extraction is needed for future closed-loop neural interfaces. This paper presents a feature extraction unit for neural oscillatory synchrony that bypasses the phase extraction step to reduce hardware complexity. Instead, the sine and cosine of the phase are directly approximated from the real and imaginary components of the signal to calculate the phase-amplitude coupling (PAC) and phase locking value (PLV). The synthesized design achieves state-of-the-art performances at 43 nW/channel and 0.006 mm(2), while maintaining sufficient accuracy for seizure detection in epileptic patients.

引用

页数：5

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