PLaNe: Reverse Engineering of Planar Layouts to Gate-Level Netlists

With the continuous advancement of semiconductor manufacturing technology and the adoption of novel techniques, reverse engineering (RE) faces new challenges. Traditional optical images based analysis methods are no longer effective due to the diminished or non-existent separation between cells and the increasing usage of upper interconnect metal layers. This study presents a graph-based approach that successfully extracts a standard cell library and gate-level netlist from a layout description. The proposed flow involves converting the layout into an undirected transistor graph. Subsequently, a directed multigraph is generated by applying predefined rules of the hybrid flow. Library reconstruction is performed through clustering and graph isomorphism, resulting in our design's flat gate-level netlist description. To evaluate the effectiveness of our approach, we conducted tests on open-source designs using two open-source libraries. The results demonstrate a cluster performance exceeding 0.9 and a standard cell reconstruction yield ranging from 0.8 to 1. Additionally, our method exhibits commendable runtime performance, and we anticipate our technology-agnostic approach to be future-proof.