Impact of a Deep Junction Coupled with a Short Channel Length on the ESD Robustness of a Grounded Gate NMOS Clamp

被引：0

作者：

Hopper, Casey ^{[1
]}

Gallerano, Antonio ^{[1
]}

Sankaralingam, Raj ^{[1
]}

机构：

[1] Texas Instruments Inc, Analog Technol Dev, 12500 TI Blvd, Dallas, TX 75243 USA

来源：

2023 45TH ANNUAL EOS/ESD SYMPOSIUM, EOS/ESD | 2023年

关键词：

D O I：

10.23919/EOS/ESD58195.2023.10287738

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Several physical insights into the multi-finger turn-on in deep junction GGNMOS devices and its implication on eventual failure current is presented with detailed experiments. The impact of junction depth to channel length ratio is found to be a key design factor in obtaining ESD robustness.

引用

页数：8

共 5 条

[1] A NOVEL HSPICE MACRO MODEL FOR THE ESD BEHAVIOR OF GATE GROUNDED NMOS AND GATE COUPLED NMOS
Yang, Shao Ming
Hema, E. P.
Sheu, Gene
Mrinal, Aryadeep
Amanullah, Md
Chen, P. A.
2015 China Semiconductor Technology International Conference, 2015,
[2] Investigation of gate to contact spacing effect on ESD robustness of salicided deep submicron single finger NMOS transistors
Oh, KH
Duvvury, C
Banerjee, K
Dutton, RW
40TH ANNUAL PROCEEDINGS: INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 2002, : 148 - 155
[3] Impact of gate-to-contact spacing on ESD performance of salicided deep submicron NMOS transistors
Oh, KH
Duvvury, C
Banerjee, K
Dutton, RW
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (12) : 2183 - 2192
[4] CHARACTERISTICS OF JUNCTION-GATE FIELD EFFECT TRANSISTOR WITH SHORT CHANNEL LENGTH
CHIU, TL
GHOSH, HN
SOLID-STATE ELECTRONICS, 1971, 14 (12) : 1307 - &
[5] Quantitative analysis of ultrashallow junction of sub-50 nm gate-length transistors: Junction depth, sheet resistance, short channel effects, and transistor performance
Buh, GH
Park, T
Yon, GH
Hong, SJ
Ryoo, CW
Yoo, JR
Lee, JW
Jee, YJ
Lee, JS
Jun, CS
Shin, YG
Chung, UI
Moon, JT
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2006, 24 (01): : 503 - 506

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