Out of Hand for Hardware? Within Reach for Software!

被引：2

作者：

Luo, Zhihong ^{[1
]}

Fu, Silvery ^{[1
]}

Amaro, Emmanuel ^{[2
]}

Ousterhout, Amy ^{[3
]}

Ratnasamy, Sylvia ^{[1
]}

Shenker, Scott ^{[1
,4
]}

机构：

[1] Univ Calif Berkeley, Berkeley, CA 94720 USA

[2] VMware Res, Palo Alto, CA USA

[3] Univ Calif San Diego, La Jolla, CA USA

[4] ICSI, New York, NY USA

来源：

PROCEEDINGS OF THE 19TH WORKSHOP ON HOT TOPICS IN OPERATING SYSTEMS, HOTOS 2023 | 2023年

关键词：

CPU stall; coroutine; profile-guided yield instrumentation; asymmetric concurrency; COROUTINES;

D O I：

10.1145/3593856.3595898

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Events that take 10s to 100s of ns like cache misses increasingly cause CPU stalls. However, hiding the latency of these events is challenging: hardware mechanisms suffer from the lack of flexibility, whereas prior software mechanisms fall short due to large overhead and limited event visibility. In this paper, we argue that with a combination of two emerging techniques - light-weight coroutines and sample-based profiling, hiding these events in software is within reach.

引用

页码：30 / 37

页数：8

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