A 10 b 50 MS/s two-stage pipelined SAR ADC in 180 nm CMOS

被引：0

作者：

沈易 ^{[1
]}

刘术彬 ^{[1
]}

朱樟明 ^{[1
]}

机构：

[1] School of Microelectronics, Xidian University

来源：

Journal of Semiconductors | 2016年 / 06期

基金：

中国国家自然科学基金;

关键词：

ADC; pipeline; SAR; MDAC;

D O I：

暂无

中图分类号：

TN792 [];

学科分类号：

080902 ;

摘要：

A 10-bit 50 MS/s pipelined SAR ADC is presented which pipelines a 5-bit SAR-based MDAC with a 6-bit SAR ADC.The 1-bit redundancy relaxes the requirement for the sub-ADC decision in accuracy.The SAR-based and "half-gain" MDAC reduce the power consumption and core area.The dynamic comparator and SAR control logic are applied to reduce power consumption.Implemented in 180 nm CMOS,the fabricated ADC achieves 56.04 dB SNDR and 5mW power consumption from 1.8 V power supply at 50 MS/s.

引用

页码：140 / 144

页数：5

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