Applying a Trusted Microelectronics Post-Silicon Verification & Validation Workflow to Legacy Integrated Circuit Design Recovery

被引:0
|
作者
Scholl, Jon [1 ]
Padro, Noah [1 ]
Patel, Yash [1 ]
McDonley, Tim [1 ]
Waite, Adam R. [1 ]
Kelley, John [1 ]
Eakins, Christian [2 ]
Juntiff, Tamara [2 ]
Kimura, Adam [1 ]
机构
[1] Battelle Mem Inst, 505 King Ave, Columbus, OH 43201 USA
[2] Air Force Res Lab, Wright Patterson AFB, OH USA
来源
2024 IEEE PHYSICAL ASSURANCE AND INSPECTION OF ELECTRONICS, PAINE 2024 | 2024年
关键词
verification; validation; trust; assurance; microelectronics; obsolescence; legacy; modernization; ASIC; FPGA; failure analysis; design recovery; CHEMICAL-MECHANICAL PLANARIZATION;
D O I
10.1109/PAINE62042.2024.10792673
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Legacy components in DoD mission critical systems have led to increasing challenges in system lifecycle management. Old lifecycle management models called for bulk replacement purchases of the component that were expected to cover all future needs. Extended service of components has undermined this paradigm. With no replacement parts or original designs, workflows for obsolescence design recovery and remanufacture become the best avenue for component replacement. This paper examines applying a workflow from a related field, post-silicon verification and validation, to the problem of obsolescence design recovery. A representative 600 nm technology node integrated circuit was chosen to demonstrate the workflow. The device was delayered, imaged with SEM and optical microscopy, and the features from active silicon up through M1 were extracted. The standard cells were extracted and analyzed, providing a path towards design netlist recovery. The workflow was then evaluated for efficacy.
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页数:7
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