An Innovative Data Compression Architecture for General Electronic Test Instruments Using Compressed Sensing Theory

General Electronic Test Instruments (GETI) include digital storage oscilloscopes, power analyzers, and spectrum analyzers, which can test signals from most military or civilian electronic equipment. GETI is a reconfigurable, integrated system based on the architecture of digital storage oscilloscopes, consisting of a mainframe and multiple boards. Different boards are assembled into different test systems. Its boards include a high-speed acquisition board, temperature acquisition board, rotational speed acquisition board, etc. Other physical quantities are converted into unified electrical parameters through different sensors. Oscilloscope recorders expand storage space to record and save information, thus posing problems with massive storage, transfer, and processing speeds. Compressive sensing (CS) demonstrates that a priori sparse signals can be accurately reduced in sparse domains with fewer samples. Therefore, this letter proposes a Data Compression Processing Architecture (DCPA) for GETI based on the theory of compressive sensing. This solution will greatly reduce the storage and transmission bandwidth of GETI and improve the real-time processing efficiency and the probability of capturing abnormal signals. First, we pre-store sparse binary matrices in a parallel logic array FPGA, and the matrix elements are multiplied with the input quantized signal and then accumulated. Since the Fourier convolution theorem, the baseband of the muxed quantized signal will obtain the full-band information of the original quantized signal. After accumulation and downsampling, the architecture accomplishes the integration and filtering of the integrating and filtering. It is worth noting that the configurable compression rate in the FPGA is jointly determined by the accumulation length and variable sparse matrix coefficients, so we pre-store the sparse matrix coefficients corresponding to a fixed compression rate (4, 8, 16) in the FPGA. We recommend using an integer multiple of 2 for the compression rate, which is friendly to structure reuse in FPGAs. The proposed architecture, which enables reconfigurable and real-time compression rates, directly reduces transmission and storage bandwidth. Finally, the compression measurements are transferred via a PCIE high-speed interface to a host computer, where the compressed signal reconstruction is done using an orthogonal matching pursuit algorithm. After extensive Monte Carlo experiments, the input signal (30-70dB) is successfully reconstructed after being compressed to 4-16 times by the system. The root mean square error between the original signal and the reconstructed signal is as low as 1.03%