Design and Hardware Implementation of Low-Latency 4-Splitting Tree-Structure-Based K-Means Clustering Trainer and Classifier Chip for Detecting Cybersecurity Attacks

被引：0

作者：

Shih, Xin-Yu ^{[1
,2
]}

Chen, Hsi-Cheng ^{[2
]}

Hung, Xin-Liang ^{[2
]}

机构：

[1] MediaTek, Dept Wireless Connect Network, Hsinchu 300, Taiwan

[2] Natl Sun Yat Sen Univ, Dept Elect Engn, Kaohsiung 804, Taiwan

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2025年 / 72卷 / 04期

关键词：

Training; Training data; Hardware; Time division multiplexing; Low latency communication; Accuracy; Machine learning; Data mining; Clustering algorithms; Semisupervised learning; Tree structure; K-means; low latency; chip architecture; cybersecurity; detection; machine learning; semi-supervised learning;

D O I：

10.1109/TCSII.2025.3543326

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this brief, we propose a first system chip architecture of 4-splitting tree-structure-based K-means clustering trainer and classifier. It mainly aims to efficiently detect cybersecurity attacks in the emerging AI-driven world. In addition, we also propose three design techniques to elaborate our chip, featuring a low-latency property in both training and classification aspects. Our developed architecture is first validated with the Xilinx FPGA platform. Furthermore, it is implemented in ASIC and well-verified with five representative cybersecurity-related datasets. The total core area with TSMC 40nm low-Vt CMOS technology only occupies 0.44 um(2), maximally operating at 434.78 MHz and possessing a maximum classification throughput of 3.48 GBps on chip. In comparison, the speed-up ratio of training and classification is up to 9.33 and 8.73 times, respectively, successfully delivering a low-latency characteristic.

引用

页码：613 / 617

页数：5