Specialized Scalar and SIMD Instructions for Error Correction Codes Decoding on RISC-V Processors

The rapid deployment of Internet-of-Things (IoT) devices for a few years has been impressive, and the progressive deployment of 5G will accelerate things even further. Indeed, this standard opens the door to a new generation of standards aimed at a convergence of networks and communication protocols (WiFi, LTE, 4G etc.). This results in the need for flexible implementations of different families of codes, such as, LPDC, NB-LDPC, turbo codes and polar codes. In this context, the work presented in this article proposes the design of a flexible instruction set processor for an IoT context. The objective is to improve the performance level of low-complexity processor cores through instruction set extensions for Error Correction Code (ECC) decoding. The approach discussed is supported by experimental results obtained based on a RISC-V architecture to which specific instruction sets have been added. The results demonstrate a reduction in the required processing clock cycles up to 44.1% for polar codes, 39.2% for LDPC codes, 21.8% for NB-LDPC codes, and 24.3% for turbo codes (4G LTE) codes with a classical Single Instruction Single Data (SISD) approach. Moreover, Single Instruction Multiple Data (SIMD) parallelization strategy enables execution time savings that are far more impressive. The number of clock cycles required to decode a data bit is reduced by 65.6% to 76.9%, with a limited hardware over-cost from 0.6% to 34% (depending on the error correction code family and the targeted RISC-V core).